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july 2016 docid029528 rev 1 1 / 13 this is information on a product in full production. www.st.com STFI15N95K5 n - channel 950 v, 0.41 typ., 12 a mdmesh? k5 power mosfet in a i2pakfp package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STFI15N95K5 950 v 0.50 12 a 30 w ? fully insulated and low profile package with increased creepage path from pin to heatsink plate ? industrys lowest r ds(on) x area ? industrys best fom (figure of merit) ? ultra - low gate charge ? 100% avalanche tested ? zener - protected applications ? switching applications description this very high voltage n - channel power mos fet is designed using mdmesh? k5 technology based on an innovative proprietary vertical structure. the result is a dramatic reduction in on - resistance and ultra - low gate charge for applications requiring superior power density and high efficiency. table 1: device summary order code marking package packing STFI15N95K5 15n95k5 i2pakfp (to - 281) tube am15572v1_no_tab d(2) g(1) s(3) 1 2 3 i 2 p akf p ( t o-281)
contents STFI15N95K5 2 / 13 docid029528 rev 1 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 9 4 package information ................................ ................................ ..... 10 4.1 i2pakfp (to - 281) package information ................................ ......... 10 5 revision hi story ................................ ................................ ............ 12
STFI15N95K5 electrical ratings docid029528 rev 1 3 / 13 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 30 v i d (1) drain current (continuous) at t c = 25 c 12 a i d (1) drain current (continuous) at t c = 100 c 7.6 a i dm (2) drain current pulsed 48 a p tot total dissipation at t c = 25 c 30 w esd gate - source human body model (r= 1,5 k, c = 100 pf) 2 kv v iso insulation withstand voltage (rms) from all three leads to external heat sink (t=1 s;t c =25 c) 2500 v dv/dt (3) peak dio de recovery voltage slope 4.5 v/ns dv/dt (4) mosfet dv/dt ruggedness 50 t j operating junction temperature range - 55 to 150 c t stg storage temperature range notes: (1) limited by maximum junction temperature. (2) pulse width limited by safe operating area. (3) i sd 12 a, di/dt 100 a/s, v ds (peak) v (br)dss (4) v ds 760 v table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 4.2 c/w r thj - amb thermal resistance junction - ambient 62.5 c/w table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repetitive or not repetitive (pulse width limited by t jmax ) 4 a e as single pulse avalanche energy (starting tj = 25 c, i d = i ar , v dd = 50 v) 124 mj
electrical characteristics STFI15N95K5 4 / 13 docid029528 rev 1 2 electrical characteristics t c = 25 c unless otherwise specified table 5: on/off - state symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 950 v i dss zero gate voltage drain current v ds = 950 v, v gs = 0 v 1 a v ds = 950 v, v gs = 0 v t c = 125 c (1) 50 a i gss gate body leakage current v gs = 20 v, v ds = 0 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 6 a 0.41 0.50 ? notes: (1) defined by design, not subject to production test. table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 v - 855 - pf c oss output capacitance - 65 - pf c rss reverse transfer capacitance - 1 - pf c o(tr) (1) equivalent capacitance time related v gs = 0 v, v ds = 0 to 760 v - 104 - pf c o(er) (2) equivalent capacitance energy related 38 - pf r g intrinsic gate resistance f = 1 mhz open drain - 6 - ? q g total gate charge v dd = 760 v, i d = 12 a v gs = 10 v (see figure 16: "test circuit for gate charge behavior" ) - 30 - nc q gs gate - source charge - 5 - nc q gd gate - drain charge - 22 - nc notes: (1) time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss (2) energy related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss table 7: swit ching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 475 v, i d = 6 a, r g = 4.7 ? v gs = 10 v (see figure 15: "test circuit for resistive load switching times" and figure 18: "unclamped inductive load test circuit" ) - 23 - ns t r rise time - 20 - ns t d(off) turn - off delay time - 62 - ns t f fall time - 11 - ns
STFI15N95K5 electrical ch aracteristics docid029528 rev 1 5 / 13 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 12 a i sdm source - drain current (pulsed) - 48 a v sd (1) forward on voltage i sd = 12 a, v gs = 0 v - 1.5 v t rr reverse recovery time i sd = 12 a, di/dt = 100 a/s, v dd = 60 v (see figure 17: "test circuit for inductive load switching and diode recovery times" ) - 444 ns q rr reverse recovery charge - 7 c i rrm reverse recovery current - 32 a t rr reverse recovery time i sd = 12 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 17: "test circuit for inductive load switching and diode recovery times" ) - 630 ns q rr reverse recovery charge - 9.2 c i rrm reverse recovery current - 29 a notes: (1) pulsed: pulse duration = 300 s, duty cycle 1.5% table 9: gate - source zener diode symbol parameter test conditions min typ. max unit v (br)gso gate - source breakdown voltage i gs = 1 ma, i d = 0 a 30 - - v the built - in back - to - back zener diodes are specifically designed to enhance the esd performance of the device. the zener voltage facilitates efficient and cost - effective device integrity protection,thus eliminating the need for additional external componentry.
electrical characteristics STFI15N95K5 6 / 13 docid029528 rev 1 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance w
STFI15N95K5 electrical characteristics docid029528 rev 1 7 / 13 figure 8 : capacitance variations figure 9 : output capacitance stored energy figure 10 : normalized gate threshold voltage vs temperature figure 11 : normalized v (br)dss vs temperature figure 12 : normalized vds vs temperature figure 13 : source - drain diode forward characteristics
electrical characteristics STFI15N95K5 8 / 13 docid029528 rev 1 figure 14 : maximum avalanche energy vs starting tj
STFI15N95K5 test circuits docid029528 rev 1 9 / 13 3 test circuits figure 15 : test circuit for resistive load switching times figure 16 : test circuit for gate charg e behavior figure 17 : test circuit for inductive load switching and diode recovery times figure 18 : unclamped inductive load test circuit figure 19 : unclamped inductive waveform figure 20 : switching time waveform
package information STFI15N95K5 10 / 13 docid029528 rev 1 4 package information in order to meet environmental requirements, st offers these devi ces in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 i2pakfp (to - 281) package informati on figure 21 : i2pakfp (to - 281) package outline 8291506 re v . c
STFI15N95K5 package information docid029528 rev 1 11 / 13 table 10: i2pakfp (to - 281) mechanical data dim. mm min. typ. max. a 4.40 4.60 b 2.50 2.70 d 2.50 2.75 d1 0.65 0.85 e 0.45 0.70 f 0.75 1.00 f1 1.20 g 4.95 5.20 h 10.00 10.40 l1 21.00 23.00 l2 13.20 14.10 l3 10.55 10.85 l4 2.70 3.20 l5 0.85 1.25 l6 7.50 7.60 7.70
revision history STFI15N95K5 12 / 13 docid029528 rev 1 5 revision history table 11: document revision history date revision changes 29 - jul - 2016 1 first release.
STFI15N95K5 docid029528 rev 1 13 / 13 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers s hould obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, select ion, and use of st products and st assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provision s different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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